1. Field of the Invention
The present invention relates to semiconductor devices, particularly a semiconductor device applied to display devices such as a liquid crystal display device and organic EL (Electro Luminescence) display device.
2. Description of the Background Art
A thin film transistor is used in a display device. As an example of such a thin film transistor, a thin film transistor of a GOLD (Gate Overlapped Lightly Doped Drain) structure disclosed in Japanese Patent Laying-Open No. 2000-252473 will be described hereinafter. An n type thin film transistor of a GOLD structure has a source region, a drain region, a channel region, a GOLD region, a gate insulation film, a gate electrode and the like formed on a glass substrate.
At a region between the channel region and the drain region, the GOLD region is formed particularly at a region located right under the gate electrode, overlapping with the gate electrode in plane. The GOLD region has an impurity concentration higher than that of the channel region, and lower than that of the drain region.
The operation of an n type thin film transistor of such a GOLD structure will be described here. By applying a predetermined positive voltage to the gate, a channel is formed at the channel region. The resistance between the source region and the drain region is reduced, allowing a current flow across the source region and the drain region.
Application of a voltage to the drain higher than that to the gate will generate a relatively large electric field at the junction of the drain side. Electrons accelerated by this electric field induce impact ionization, whereby a pair of an electron and hole is generated. Impact ionization is repeated to increase the pairs of electrons and holes, causing increase in the drain current to result in avalanche breakdown. The drain voltage at this stage becomes the source-drain breakdown voltage.
In the present description, the source-drain breakdown voltage corresponds to the drain voltage when 0V is applied to the gate electrode and the drain current across the source and drain is 0.1 μA per 1 μm gate width.
The GOLD region is provided to improve such source-drain breakdown voltage, and is formed overlapping with the gate electrode at a region between the channel region and drain region. Generally, the impurity concentration of the GOLD region is set lower than that of the drain region. According to such a configuration, the electric field in the proximity of the drain is alleviated at the junction between the channel region and GOLD region, so that impact ionization can be suppressed. Therefore, the source-drain breakdown voltage can be improved.
By setting the length of the GOLD region in the direction of the channel length longer, the source-drain breakdown voltage can be further improved.
The conventional semiconductor device has a problem set forth below. In a conventional semiconductor device, the GOLD length of the GOLD region is set identical with respect to all the N channel type thin film transistors of a GOLD structure. Therefore, it was necessary to set a long GOLD length in conformance with the n channel type thin film transistor that needs the highest source-drain breakdown voltage among the thin film transistors formed at the TFT (Thin Film Transistor) array substrate. In other words, a long GOLD length had to be set in conformance with the n channel type thin film transistor to which the highest voltage is applied.
This means that an n channel type thin film transistor that does not need such a long GOLD length since the applied voltage is relatively low was also set to have a long GOLD length.
Therefore, the area occupied by the thin film transistors is increased since a long GOLD length is set even for a thin film transistor that does not essentially require such a long GOLD length. This induces the problem that the number of TFT array substrates fabricated from one glass substrate is reduced to increase the fabrication cost.